? semiconductor components industries, llc, 2004 july, 2004 ? rev. 2 1 publication order number: max707/d max707, max708 p supervisory circuits the max707/708 are cost?effective system supervisor circuits designed to monitor v cc in digital systems and provide a reset signal to the host processor when necessary. no external components are required. the reset output is driven active within 20 sec of v cc falling through the reset voltage threshold. reset is maintained with 200 ms of delay time after v cc rise above the reset threshold. the max707/708 have a low quiescent current of 12 at v cc = 3.3 v, an active?high reset and active?low reset with a push?pull output. the output is guaranteed valid down to v cc = 1.0 v. the max707/708 have a manual reset mr input and a +1.25 v threshold detector for power?fail input pfi. these devices are available in a micro8 and soic?8 package. features ? pb?free packages are available ? precision supply?voltage monitor max707: 4.63 v reset threshold voltage max708: standard reset threshold voltages (typical): 4.38 v, 3.08 v, 2.93 v, 2.63 v ? reset threshold available from 1.6 v to 4.9 v with 100 mv increments (factory option) ? 200 ms (typ) reset timeout delay ? 12 a (v cc = 3.3 v) quiescent current ? active_high and active_low reset output ? guaranteed reset_l and reset output valid to v cc = 1.0 v ? voltage monitor for power?fail or low?battery warning ? 8 pin soic or micro8 package applications ? computers ? embedded system ? battery powered equipment ? critical p power supply monitor pin configuration 1 reset 8 nc 2 reset 3 mr 4 v cc 7 pfo 6 pfi 5 gnd (top view) micro8 cua suffix case 846a 1 8 soic?8 esa suffix case 751 1 8 micro8 1 mr 8 reset 2 3 gnd 4 pfi 7 reset 6 nc 5 pfo (top view) soic?8 see detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. ordering information xxxxx alyw 1 8 xxx alyw 1 8 marking diagrams xxxxx = specific date code al = assembly lot code y = year w = week http://onsemi.com xxx = specific device code a = assembly location l = wafer lot y = year w = week v cc
max707, max708 http://onsemi.com 2 figure 1. representative block diagram ? + ? + reset generator reset reset pfo mr pfi v cc v cc 1.25 v gnd v th maximum ratings (note 1) rating symbol value unit supply voltage v cc 6.0 v output voltage v out ?0.3 to (v cc + 0.3) v output current (all outputs) i out 20 ma input current (v cc and gnd) i in 20 ma thermal resistance junction?to?air micro8 soic?8 r ja 248 187 c/w operating ambient temperature t a ?40 to +85 c storage temperature range t stg ?40 to +125 c latchup performance positive negative i latchup 300 280 ma maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 1. this device series contains esd protection and exceeds the following tests: human body model 2000 v per mil?std?883, method 3015. machine model method 200 v. 2. the maximum package power dissipation limit must not be exceeded. p d t j(max) t a r ja with t j(max) = 150 c
max707, max708 http://onsemi.com 3 electrical characteristics (v cc = 1.0 v to 5.5 v, t a = ?40 c to +85 c, unless otherwise noted. typical values are at t a = 25 c, v cc = 3.3 v.) characteristics symbol min typ max unit operating voltage range v cc 1.0 ? 5.5 v supply current v cc = 3.3 v v cc = 5.5 v i cc ? ? 12 16 22 28 a reset threshold max707 t a = +25 c t a = ?40 c to +85 c max708 t a = +25 c t a = ?40 c to +85 c max708t t a = +25 c t a = ?40 c to +85 c max708s t a = +25 c t a = ?40 c to +85 c max708r t a = +25 c t a = ?40 c to +85 c v th 4.56 4.50 4.31 4.25 3.03 3.00 2.89 2.85 2.59 2.55 4.63 4.38 3.08 2.93 2.63 4.70 4.75 4.45 4.50 3.13 3.15 2.97 3.00 2.67 2.70 v reset threshold hysteresis v hys ? 0.01 v th ? mv v cc falling reset delay (v cc = v th + 0.2 v to v th ? 0.2 v) t pd ? 20 ? s reset active timeout period t rp 140 200 330 ms reset_l, reset_h output low voltage v cc 1.0 v, i ol = 100 a v cc 2.7 v, i ol = 1.2 ma v cc 4.5 v, i ol = 3.2 ma v ol ? ? ? ? ? ? 0.3 0.3 0.3 v reset_l, reset_h output high voltage v cc 1.0 v, i oh = 50 a v cc 2.7 v, i oh = 500 a v cc 4.5 v, i oh = 800 a v oh 0.8 v cc 0.8 v cc 0.8 v cc ? ? ? ? ? ? v mr_l pull?up resistance r mri 50 ? ? k mr_l pulse width (v th (max) v cc 5.5 v) t mr 1.0 ? ? s mr_l glitch rejection (v th (max) v cc 5.5 v) ? ? 0.1 ? s mr_l high_level input threshold (v th (max) v cc 5.5 v) v ih 0.7 v cc ? ? v mr_l low_level input threshold (v th (max) v cc 5.5 v) v il ? ? 0.3 v cc v mr_l to reset_l and reset_h output delay (v th (max) v cc 5.5 v) t md ? 0.2 ? s pfi input threshold (v cc = 3.3 v, pfi falling) ? 1.20 1.25 1.3 v pfi input current ? ?250 0.01 250 na pfi to pfo delay (v cc = 3.3 v, v overdrive = 15 mv) ? ? 3.0 ? s pfo_l output low voltage v cc = 2.7 v, i ol = 1.2 ma v cc = 4.5 v, i ol = 3.2 ma v ol ? ? ? ? 0.3 0.3 v pfo_l output high voltage v cc = 2.7 v, i oh = 500 a v cc = 4.5 v, i oh = 800 a v oh 0.8 v cc 0.8 v cc ? ? ? ? v
max707, max708 http://onsemi.com 4 pin description (pin no. with parentheses is for micro8 package.) pin no. symbol description 1 (3) mr manual reset input. mr can be driven from ttl/cmos logic or from a manual reset switch. this input, when floating, is internally pulled up to v cc with 50 k resistor. 2 (4) v cc supply voltage: c = 100 nf is recommended as a bypass capacitor between v cc and gnd. 3 (5) gnd ground reference 4 (6) pfi power fail voltage monitor input. when pfi is less than 1.25 v, pfo goes low. connect pfi to gnd or v cc when not used. 5 (7) pfo power fail monitor output. when pfi is less than 1.25 v, it goes low and sinks current. otherwise, it remains high. 6 (8) nc non-connective pin 7 (1) reset active low reset can be triggered by v cc below the threshold level or by a low signal on mr . it remains low for 200 ms (typ.) after v cc rises above the reset threshold. 8 (2) reset active high reset output the inverse of reset one. 16 12 18 10 14 0 20 8 6 4 2 3.0 0.5 1.0 0 i out , output sink current (ma) 0 figure 2. max707/708 series 1.60 v reset output sink current vs. output voltage figure 3. max707/708 series 1.60 v reset output source current vs. input voltage figure 4. max707/708 series 2.93 v reset output sink current vs. output voltage figure 5. max707/708 series 2.93 v reset output source current vs. input voltage v in , input voltage (v) i out , output source current (ma) v out , output voltage (v) 2.0 2.0 0.0 1.0 6.0 2.0 3.0 4.0 5.0 t a = 25 c v in ? 1.0 v v in ?1.5 v v in ? 0.5 v v out = v in ? 2.0 v 2.5 1.5 0.5 1.0 1.5 20 3.0 12 0 i out , output source current (ma) 0 v in , input voltage (v) 16 2.0 18 14 10 1.0 4.0 4 8 6 2 5.0 6.0 i out , output sink current (ma) 12 0 10 4 8 6 2 0.5 0 v out , output voltage (v) 2.0 1.0 1.5 2.5 3.0 v in = 2.5 v v in = 2.0 v v in = 1.5 v t a = 25 c v in = 1.0 v v in = 1.5 v t a = 25 c t a = 25 c v in ? 1.0 v v in ? 1.5 v v in ? 0.5 v v out = v in ? 2.0 v
max707, max708 http://onsemi.com 5 16 12 18 10 14 0 20 8 6 4 2 30 25 15 20 10 5 0 figure 6. max707/708 series 4.90 v reset output sink current vs. output voltage v out , output voltage (v) figure 7. max707/708 series 4.90 v reset output source current vs. input voltage v in , input voltage (v) i out , output sink current (ma) i out , output source current (ma) 0.0 4.0 3.0 2.0 1.0 5.0 0.0 1.0 6.0 2.0 3.0 4.0 5.0 t a = 25 c v in ? 1.0 v v in ? 1.5 v v in ? 0.5 v t a = 25 c v in = 4.0 v v in = 3.0 v v in = 2.0 v v out = v in ? 2.0 v figure 8. max707/708 series 1.60 v detector threshold voltage vs. temperature ?50 1615 25 1595 0 ?25 v det , detector threshold voltage (volts) 1585 1625 t a , ambient temperature ( c) 1605 100 v det? v det+ 1620 1610 1600 1590 50 75 v det , detector threshold voltage (volts) 5000 4980 4960 4880 5020 ?50 ?25 100 4920 4900 0255075 v det? v det+ figure 9. max707/708 series 4.90 v detector threshold voltage vs. temperature t a , ambient temperature ( c) 4940 30 figure 10. max707/708 series 2.93 v detector threshold voltage vs. temperature t a , ambient temperature ( c) t pd , v cc , falling reset delay ( s) ?40 40 60 20 080 ?20 20 35 15 25 0 40 45 v th = 4.90 v v th = 2.93 v v th = 1.60 v 10 5 v det , detector threshold voltage (volts) 3110 3100 3090 3060 3120 t a , ambient temperature ( c) ?50 ?25 100 3080 3070 0255075 v det? v det+ figure 11. max707/708 series v cc falling reset delay vs. temperature
max707, max708 http://onsemi.com 6 applications information microprocessor reset to generate a processor reset, the manual reset input allows different reset sources. a pushbutton switch can be one of these. it is effectively debounced by the 1.0 s minimum reset pulse width. as mr is ttl/cmos logic compatible, it can be driven by an external logic line. v cc reset figure 12. reset and mr timing mr v th v th t rp t rp t md t mr v cc transient rejection the max707/708 provides accurate v cc monitoring and reset timing during power?up, power?down, and brownout/sag conditions, and rejects negative glitches on the power supply line. figure 13 shows the maximum transient duration vs. maximum negative excursion (overdrive) for glitch rejection. for a given overdrive, the point of the curve is the maximum width of the glitch allowed before the device generates a reset signal. t ransient immunity can be improved by adding a capacitor (100 nf for example) in close proximity to the v cc pin of the max707/708. 300 250 150 200 100 50 0 figure 13. maximum transient duration vs. overdrive for glitch rejection at 25 c reset comparator overdrive (mv) maximum transient duration ( s) 10 90 70 50 30 110 130 150 v th v cc duration overdrive v th = 4.90 v v th = 3.08 v v th = 1.60 v
max707, max708 http://onsemi.com 7 reset signal integrity during power?down the max707/708 reset output is valid until v cc falls below 1.0 v. then, the output becomes an open circuit and no longer sinks current. this means cmos logic inputs of the p will be floating at an undetermined voltage. most digital systems are completely shutdown well above this voltage. however, in the case reset must be maintained valid to v cc = 0 v, a pull down resistor must be connected from reset to ground to discharge stray capacitances and hold the output low (figure 14). this resistor value, though not critical, should be chosen large enough not to load reset and small enough to pull it to ground. r = 100 k will be suitable for most applications. reset figure 14. ensuring reset valid to v cc = 0 v v cc gnd max707/708 r 100 k interfacing with ps with bidirectional i/o pins some ps have bidirectional reset pins. if, for example, the reset output is driven high and the p wants to put it low, indeterminate logic level may result. this can be avoided by adding a 4.7 k resistor in series with the output of the max707/708 (figure 15). if there are other components in the system that require a reset signal, they should be buf fered so as not to load the reset line. if the other components are required to follow the reset i/o of the p, the buffer should be connected as shown with the solid line. reset reset figure 15. interfacing to bidirectional reset i/o gnd max707/708 v cc gnd v cc buffer p buffered reset to other system components 4.7 k monitoring additional supply levels when connecting a voltage divider to pfi and adjusting it properly, you can monitor a voltage different than the unregulated dc one. as shown in figure 16, to increase noise immunity, hysteresis may be added to the power?fail comparator just by a resistor between pfo and pfi. not to unbalance the potential divider network, r3 should be 10 times the sum of the two resistors r1 and r2. if required, a capacitor between pfi and gnd will reduce the sensitivity of the circuit to high?frequency noise on the line being monitored. the pfo output may be connected to mr input to generate a low level on the reset when v cc _1 drops out of tolerance. thus a reset is generated when one of the two voltages is below its threshold level. max707/708 figure 16. monitoring additional supply levels gnd v cc gnd v cc p reset mr pfo pfi reset r1 r2 r3 v cc_1 v cc_2 v cc_3 pfo v cc_1 v cc_2 0 v 0 v v l v h v l 1.25 r1 1.25 r2 1.25 v cc_2 r3 v h 1.25 (1 r1 r2 r3 r2 r3 ) v hys v h v l r1 v cc_2 r3
max707, max708 http://onsemi.com 8 ordering information device marking package shipping 2 max707esa?t s707 soic?8 2500 tape & reel max708esa?t s708 soic?8 2500 tape & reel max708xesa?t, g* (note 3) s708x soic?8 2500 tape & reel max707cua?t sac micro8 4000 tape & reel max708cua?t sad micro8 4000 tape & reel max708xcua?t, g* (note 3) say (note 4) micro8 4000 tape & reel 2for information on tape and reel specifications,including part orientation and tape sizes, please refer to our tape and reel p ackaging specifications brochure, brd8011/d. * the ago suffix indicates pb?free package available. 3. the axo denotes a suffix for v cc threshold ? see table 1. 4. the ayo denotes a suffix for v cc threshold ? see table 2. table 1. suffix axo suffix reset v cc threshold (v) t 3.08 s 2.93 r 2.63 table 2. suffix ayo suffix reset v cc threshold (v) e 3.08 f 2.93 g 2.63
max707, max708 http://onsemi.com 9 package dimensions micro8 case 846a?02 issue f *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 8x 8x 6x mm inches scale 8:1 1.04 0.041 0.38 0.015 5.28 0.208 4.24 0.167 3.20 0.126 0.65 0.0256 s b m 0.08 (0.003) a s t dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 2.90 3.10 0.114 0.122 c --- 1.10 --- 0.043 d 0.25 0.40 0.010 0.016 g 0.65 bsc 0.026 bsc h 0.05 0.15 0.002 0.006 j 0.13 0.23 0.005 0.009 k 4.75 5.05 0.187 0.199 l 0.40 0.70 0.016 0.028 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. 846a-01 obsolete, new standard 846a-02. ?b? ?a? d k g pin 1 id 8 pl 0.038 (0.0015) ?t? seating plane c h j l
max707, max708 http://onsemi.com 10 package dimensions soic?8 case 751?07 issue ab *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 max707/d micro8 is a trademark of international rectifier. literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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